The Hardware Engineer's Bible

Solution:

Use two 2:1 MUXes for the first stage (controlled by S0) and one 2:1 MUX for the second stage (controlled by S1).

        I0 ──┐
             ├─── MUX1 ──┐
        I1 ──┘           │
             S0          ├─── MUX3 ─── Output
        I2 ──┐           │      S1
             ├─── MUX2 ──┘
        I3 ──┘
             S0
                            

Explanation:

// Combinational Logic
always @(*) begin
    y = a & b;  // Blocking
end

// Sequential Logic
always @(posedge clk) begin
    q <= d;  // Non-blocking
end

Definition:

A state where a flip-flop output hovers between logic 0 and 1, unable to settle to a valid logic level within the required time.

MTBF (Mean Time Between Failures):

Statistical measure of how often metastability failures occur. Formula:

Where: t_r = resolution time, τ = time constant, f_c = clock frequency, f_d = data frequency

Mitigation Strategies:

• Use multi-stage synchronizers (2-FF or 3-FF)
• Increase resolution time
• Use handshaking protocols for CDC
• Employ Gray code for multi-bit signals

Gray Code Approach:

Compare Read/Write pointers in Gray code to avoid metastability issues when crossing clock domains.

// Gray Code Conversion
gray = binary ^ (binary >> 1);

// Full Logic
full = (wptr_gray[N:N-1] != rptr_gray_sync[N:N-1]) && 
       (wptr_gray[N-2:0] == rptr_gray_sync[N-2:0]);

// Empty Logic
empty = (wptr_gray_sync == rptr_gray);

Setup Violation Fixes:

• Reduce clock frequency - Increases clock period
• Optimize combinational logic - Reduce delay in data path
• Increase voltage - Speeds up transistor switching
• Resize gates - Use faster cells in critical path
• Pipeline the design - Break long paths into stages

Hold Violation Fixes:

• Add delay buffers - Increase data path delay
• Increase clock skew - Delay clock to capturing flop
• Resize gates - Use slower cells in data path

Setup Time:     Hold Time:
    ___             ___
CLK    |___|    CLK    |___
       ↑               ↑
    [Setup]        [Hold]
Data must be    Data must be
stable BEFORE   stable AFTER
                            

Design Challenge:

Detect sequence 1011. Contrast Overlapping vs Non-overlapping detection.

State Transition (Moore Machine - Overlapping):

State  |  In=0  |  In=1  | Output
-------|--------|--------|-------
S0 (R) |  S0    |  S1    |   0
S1 (1) |  S2    |  S1    |   0
S2 (10)|  S0    |  S3    |   0
S3(101)|  S2    |  S4    |   0
S4(11) |  S2    |  S1    |   1  <-- Detection!
                                

Schematic:

   Enable ──┐    ____
            ├──>|    \
   CLK ─────┤   |LAT  |──┐   ____
            │   |____/   └──|    \
            |               | AND |─── Gated_CLK
   CLK ─────────────────────|____/
                                

Why the Latch?

To prevent glitches on the output clock. The latch ensures the Enable signal is stable (Low or High) during the entire active phase of the clock. Without it, if Enable acts while CLK is high, you'd chop the clock pulse (glitch).

Why FinFET?

At nodes < 20nm, Planar MOSFETs suffer from excessive Short Channel Effects (SCE).

• Better Control: Gate wraps around the channel on 3 sides (Top, Left, Right).
• Lower Leakage: Significantly reduces off-state current ($I_{off}$).
• Higher Drive Current: Larger effective width in smaller footprint.

What is DIBL?

Drain-Induced Barrier Lowering: As Drain voltage ($V_{ds}$) increases, the depletion region of the drain expands and lowers the potential barrier at the source.

Result: Channel turns on at a lower $V_{gs}$ (Threshold voltage $V_{th}$ decreases), causing leakage.

CMOS Inverter VTC (Voltage Transfer Characteristic):

Curve plotting $V_{out}$ vs $V_{in}$.

• Region 1: NMOS OFF, PMOS Linear (Output = VDD)
• Region 2: NMOS Sat, PMOS Linear
• Region 3 (Switching Point $V_M$): Both Saturation
• Region 4: NMOS Linear, PMOS Sat
• Region 5: NMOS Linear, PMOS OFF (Output = GND)

Impact of W/L Ratio:

If you increase $(W/L)_{PMOS}$: The PMOS becomes stronger. It pulls the output HIGH more easily.
Result: The switching threshold $V_M$ shifts to the RIGHT (towards VDD).

Classic 5-Stage RISC Pipeline:

Pipeline Hazards:

• Structural: Resource conflicts (e.g., single memory for I&D)
• Data: RAW, WAR, WAW dependencies
• Control: Branch instructions causing stalls

MESI Protocol States:

State Transitions:

• Read Miss: I → E (if no other cache has it) or I → S (if shared)
• Write Hit: E → M, S → M (invalidate other caches)
• Write Miss: I → M (invalidate all other copies)
• Snoop Read: M → S (write back to memory), E → S

DMA Transfer Process:

Advantages:

• Frees CPU for other tasks during I/O
• Higher throughput for bulk transfers
• Reduced CPU overhead

DMA Modes:

• Burst Mode: DMA takes bus until transfer complete
• Cycle Stealing: DMA transfers one word at a time
• Transparent Mode: DMA uses bus only when CPU doesn't need it

Problem:

64KB Cache, 64-byte line size, 4-way Set Associative, 32-bit Address. Find Offset, Index, Tag bits.

Solution Steps:

1. Offset: Depends on block size. $\log_2(64) = 6$ bits.
2. Number of Sets: $$ \text{Total Lines} = \frac{64KB}{64B} = 1024 \text{ lines} $$ $$ \text{Sets} = \frac{1024}{4 \text{ (ways)}} = 256 \text{ sets} $$
3. Index: Depends on number of sets. $\log_2(256) = 8$ bits.
4. Tag: Remaining bits. $32 - (8 + 6) = 18$ bits.

Topic 5 Scenario:

Producer: 200MHz, 80% duty cycle. Consumer: 150MHz continuous. Burst: 1000 items.

Formula:

$$ \text{Depth} = \text{Burst} \times (1 - \frac{\text{Consumer Rate}}{\text{Producer Rate}}) $$

Calculation:

• Producer effective rate = $200 \times 0.8 = 160 \text{ MHz}$.
• Wait, logic check: Producer writes 1000 items at 200MHz peak? Or average?
  Correct Approach: Time to write burst = $1000 / 200\text{MHz} = 5\mu s$.
  Consumer reads in $5\mu s$ = $150\text{MHz} \times 5 = 750$.
  Buffer needed = $1000 - 750 = 250$.

When to use LDO?

For sensitive analog/RF circuits (PLLs, ADCs) that need clean voltage (low noise), or when $V_{in}$ is very close to $V_{out}$ (high efficiency region).

When to use Buck?

For high-power digital cores (CPU/GPU) where efficiency (>90%) is critical and noise is manageable.

Sequence of Events:

1. Assertion: Peripheral asserts IRQ line.
2. Context Save: Push PC and CPSR to Stack.
3. Vector Fetch: Jump to ISR address.
4. Execute ISR: Run driver code.
5. Context Restore: Pop PC/CPSR (RTE instruction).

Task:

Recursively find all .v files and replace "module old_name" with "module new_name".

Solution:

import os

root_dir = "./design"
for dirpath, _, filenames in os.walk(root_dir):
    for fname in filenames:
        if fname.endswith(".v"):
            path = os.path.join(dirpath, fname)
            
            with open(path, "r") as f:
                content = f.read()
            
            if "module old_name" in content:
                new_content = content.replace("module old_name", "module new_name")
                with open(path, "w") as f:
                    f.write(new_content)
                print(f"Updated {path}")

Scenario:

Regression output results.csv has columns: TestName, Status (PASS/FAIL), Runtime.

Tasks:

1. Count PASS/FAIL/TOTAL.
2. Find test with max runtime.

Pandas Solution:

import pandas as pd

df = pd.read_csv("results.csv")

# 1. Counts
counts = df['Status'].value_counts()
print(counts)

# 2. Max Runtime
slowest_test = df.loc[df['Runtime'].idxmax()]
print(f"Slowest: {slowest_test['TestName']} ({slowest_test['Runtime']}s)")

Pure Python Solution (No Libraries):

import csv

max_runtime = 0
slowest = ""
counts = {"PASS": 0, "FAIL": 0}

with open("results.csv", "r") as f:
    reader = csv.DictReader(f)
    for row in reader:
        counts[row['Status']] += 1
        curr_time = float(row['Runtime'])
        if curr_time > max_runtime:
            max_runtime = curr_time
            slowest = row['TestName']

Goal:

Read a Verilog module header and print an instantiation template.

Input:

module my_design (
    input clk,
    input rst_n,
    input [31:0] data_in,
    output reg done
);

Python Script:

import re

text = """...verilog code string..."""

# Regex to capture direction, width (optional), and name
# Groups: 1=dir, 2=width, 3=name
pattern = r"\s*(input|output)\s+(?:reg\s+)?(?:(\[[^\]]+\])\s+)?(\w+)"

matches = re.findall(pattern, text)

print("my_design u_dut (")
for i, (direction, width, name) in enumerate(matches):
    comma = "," if i < len(matches)-1 else ""
    print(f"    .{name}({name}){comma}")
print(");")